1. Field of the Invention
The present invention relates to an image display device and image display panel wherein a so-called point sequential clock driving system is applied in a drive circuit.
2. Description of the Related Art
FIG. 1 and FIG. 2 are block diagrams of an example of the configuration of an image display panel wherein the point sequential clock driving system is applied.
Image display panels 1A and 1B comprise, as shown in FIG. 1 and FIG. 2, a pixel portion 2 arranged with pixels in matrix, and a vertical drive circuit (V.DRV) 3, a horizontal drive circuit (H.DRV) 4 and a precharge circuit (P.CHG) 5 as a variety of circuits connected to the pixel portion 2.
The pixel portion 2 uses, for example, a liquid crystal cell as a display element (pixel) of an image. Each liquid crystal cell is provided with a liquid crystal element and a Thin Film Transistor (TFT) which is turned on when displaying for supplying a video signal SP to one electrode (pixel electrode) of the liquid crystal element. While not particularly shown, gates of the TFT on each row (one display line) are connected to a gate line and either one of sources and drains of the TFT on each column are connected to a data line. The vertical drive circuit (V.DRV) 3 scans (sequentially drives every predetermined time),gate lines when displaying an image, and the horizontal drive circuit (H.DRV) 4 point-sequentially supplies display data of an amount of one display line to the data line (horizontal scan) in a driving time of the gate line (horizontal scan period). By combining the horizontal scan and the vertical scan, an image of one screen is displayed on the pixel portion 2.
In the point sequential clock driving system, the horizontal drive is controlled by a horizontal clock.
In the configuration example shown in FIG. 1, a clock generation portion 6 inside the panel generates horizontal clocks (hereinafter, referred to as drive clocks) DCK1 and DCK2 having a pulse width of a smaller duty ratio and reversed phases to each other and their inverted drive clocks DCK1X and DCK2X based on horizontal clocks HCK and HCKX having reversed phases to each other input from outside. When the horizontal drive circuit (H.DRV) 4 receives a horizontal start pulse (HST: not shown) from the outside or the clock generation portion 6, it shifts the horizontal start pulse (HST) by a built-in shift register driven by input horizontal clocks HCK and HCKX having reversed phases to each other, extracts drive clocks DCK1 and DCK2 based on the shifted pulse and generates a drive pulse for driving a data sampling switch (HSW). The data sampling switch (HSW) is, while not particularly illustrated, provided to an output stage of the horizontal drive circuit (H.DRV) 4 or a video signal input portion of the pixel portion 2 and samples point-sequentially an input video signal by the horizontal drive pulse. Note that, in FIG. 1, a clock buffer circuit 7 is provided in accordance with need. In this case, the clock buffer circuit 7 adjusts the horizontal clock HCK by using the horizontal clock HCKX, adjusts the drive clock DCK1 by using the drive clock DCK1X, adjusts the drive clock DCK2 by using the drive clock DCK2X and outputs the adjusted drive clocks DCK1 and DCK2. Also, the clock buffer circuit 7 converts a voltage level of various clocks to a voltage suitable to panel driving.
On the other hand, in the configuration example shown in FIG. 2, the horizontal clock HCK and its inverted clock HCKX, drive clocks DCK1 and DCK2 and their inverted drive clocks DCK1X and DCK2X for driving the horizontal drive circuit (H.DRV) 4 are all given from outside of the panel.
Note that a start pulse and a clock for driving the vertical drive circuit (V.DRV) 3 are omitted in FIG. 2. Also in this case, a clock buffer circuit 7 having the same function as that in FIG. 1 is provided in accordance with need.
In an image display device of the point sequential driving system, in the case where one-channel video signal SP is input, it becomes difficult to secure a sufficient sampling time for successively sampling all pixels in a limited horizontal scan period (1H period) particularly when the number of pixels in the horizontal direction increases as the definition gets higher.
Thus, to secure a sufficient sampling time for one pixel, as shown in FIG. 13, there is known an M-phase driving system of inputting M-channel video signals SP (M is an integer of two or more) in parallel and, in unit of M-number of sampling switches corresponding to M-number of pixels in the horizontal direction, driving M-number of sampling switches HSW in one unit by one sampling pulse DPodd or DPeven at a time so as to perform successive writing in unit of M pixels.
Here, a pixel display unit configured by a group of pixels connected to M-number of data lines (normally an even number, for example, 6 or 12) in the horizontal direction, to which a video signal is supplied at a time will be referred to as a “section” below.
In the above horizontal driving method of pixels, the drive pulses DPodd and DPeven as data sampling pulses are generated by extracting pulses from the drive clocks DCK1 and DCK2 having reversed phases to each other and a smaller duty ratio than that of the horizontal clocks HCK and HCKX. In the case of driving the drive clocks having reversed phases to each other, one of a section of an odd number, that is, (2N−1) (N is a natural number) and a section of an even number, that is, 2N is driven by a drive pulse extracted from the drive clock DCK1 and the other is driven by a drive pulse extracted from the drive clock DCK2. In FIG. 13, the drive pulse driving the odd section is indicated by DPodd and the drive pulse driving the even section is indicated as DPeven.
The reason of using the drive clocks DCK1 and DCK2 having reversed phases to each other is because the sampling number of two times per one clock cycle is possible, so that a sampling frequency can be doubled from a horizontal driving frequency.
Also, the reason of making the duty ratio of the drive clocks DCK1 and DCK2 small is to secure a margin for a ghost on the display screen caused by an overlap of sampling pulses and phase deviation (drift) of pulses and to prevent deterioration of image quality caused thereby. Below, the causes of deteriorating image quality will be explained.
FIG. 14A to FIG. 14D are signal waveforms in the case pulses extracted not from the drive pulses but from the horizontal clocks HCK and HCKX are used for data sampling.
Since more or less roundness is generated in the clock pulse shape due to resistance of wiring and a parasitic capacitance from generation of the horizontal clocks HCK and HCKX to extraction of pulses, a tailing shape arises more or less in the extracted pulses Vh1 to Vh3 as shown in FIG. 14A to FIG. 14C. As a result, the waveforms overlap between the sampling pulses Vh1 and Vh2 and between sampling pulses Vh2 and Vh3.
Generally, at a moment of turning on the horizontal sampling switch HSW, induced noise IDN is more or less generated on a video line as shown in FIG. 14D via a connection capacitance due to relationship of potentials of the video line to be supplied a video signal and a data line.
Under such a circumstance, when sampling pulses Vh1 and Vh2 or Vh2 and Vh3 are overlapped as explained above, induced noise IND generated by turning on the sampling switch HSW of the next section overlaps with the sampling period and unfavorably holds it. As a result, the holding potential, that is, a potential of pixel data after sampling becomes uneven and deteriorates the image quality.
An active element of variety of circuits incorporated in the panel is composed of a TFT formed on the same substrate as the TFT of the pixel portion 2. The TFT has larger characteristic variation comparing with a bulk transistor and the characteristic is easily changed by aging and other heat treatment. When characteristic of the TFT changes, particularly a sampling timing by the data sampling switch HSW is deviated. The deviation of the sample timing causes a phenomenon called “ghost”, that is, an undesirable image generated by deviating by certain dots from a correct image position overlaps with the correct image on the display screen.
FIG. 15A to FIG. 15C are timing charts of a signal when ghost arises, and FIG. 15D shows the display screen.
A video signal Sig(N+1) in the (N+1) section among a video signal divided to M sections is shown in FIG. 15A. Normally, a pulse of a video signal deforms more or less, such as a tailing shape, due to affection by delay. A sampling pulse Vh(N+1) of the deformed video signal is shown in FIG. 15C, and a sampling pulse Nh(N) in the N section, which is one section before, is shown in FIG. 15B. In FIG. 15B and FIG. 15C, a broken line indicates a pulse in an initial state and a solid line indicates a pulse after drifting by aging, etc. When assuming that the video signal is sampled at rising of a sampling pulse and held at falling, the video signal Sig(N+1) in the (N+1) section is sampled and held in both of the N section and (N+1) section by the drift of the pulse and, furthermore, appears on the display screen at a level of an intermediate gradation color (gray).
Here, the ghost margin is generally a distance between a focused section and a section of a pulse affecting as a ghost thereof and expressed by the number of sections between the two. In an example in FIG. 15, the ghost arises in the adjacent section, so that the ghost margin is 0 (unit is section).
By generating the sampling pulse by extracting a pulse not from the horizontal clock itself but from a drive clock having a smaller duty ratio generated from the horizontal clock, the overlap of pulse waveforms and the margin to ghost explained above can be increased without raising the horizontal drive frequency. The image display panel shown in FIG. 1 and FIG. 2 realizes highly fine image expression by a technique of using four clocks HCK, HCKX, DCK1 and DCK2 and supplying, for example, a 6-phase or 12-phase video signal.
Along with an increase of kinds of image display panels and a reduction in costs, a cost reduction by commonality of components becomes necessary.
For example, to perform M-phase driving on a video signal, a sample hold IC used in common has been developed, wherein M-number of (for example 6) sample hold circuits are incorporated, the input video signal SP is divided to M-number of outputs at a timing controlled by a timing control signal of the horizontal drive circuit, and M-number of signals Sig1 to SigM are output at a time at a timing when the M-number of outputs are all prepared. Further in detail, a method wherein an Extended Graphics Array (XGA) display standard panel conventionally driven by 12-dot simultaneous sampling is driven by 6-dot simultaneous sampling in the same way as in the Super Video Graphics Array (SVGA) display standard panel has been developed. Due to this, the sample hold IC required two for each of RGB in 12-dot simultaneous sampling is required one for each by performing 6-dot simultaneous sampling, that is, the number is halved and the cost is reduced for that amount.
When realizing a panel having horizontal pixels of K times (K is an integer of 2 or more) as much as that of a panel conventionally used by the circuit by using a video signal drive circuit for M-number simultaneous sampling, a width of the sampling pulse has to be simply 1/K to be used. Namely, in the above example, to realize horizontal driving of an XGA panel by using one SVGA sample hold IC capable of performing 6-dot simultaneous sampling, widths of the drive pulses DPodd and DPeven have to be ½.
To realize the above non-overlap sampling and ghost margin securement under this constraint, the drive pulse in the above example becomes a narrow pulse having a width of, for example, 30 to 45 nsec or so. This pulse width is remarkably narrow comparing with a drive pulse width of 150 nsec in the conventional XGA panel realizing 12-dot simultaneous sampling by using two sample hold ICs. Below, the panel driving using a pulse having a width of 50 nsec or less as such will be referred to as “narrow pulse driving”.
In an XGA panel driven by the narrow pulse driving, there arose a phenomenon that a vertical stripe pattern of every sampling dot number of the sample hold IC, that is, every 6 dots appeared on the display screen. This phenomenon has been observed conventionally, which has been known to be caused by a characteristic difference of two sampling hold ICs. However, it is obvious that it is not caused by the characteristic difference of the ICs because the sample hold IC is provided one here.